The Implementation Of FPGA For UWB Receiver Based On TURBO Iteration

Ultra-Wideband (UWB) is a novel short-distance wireless communication technique, which has a wide bandwidth up to GHz and is able to provide a high data rate up to Mbps, thus it becomes a hot spot in current researches. However, there are some key problems which must be solved before it matures, one of that is the receiver's hardware implementation. It requires not only a good performance, but also a simple structure.In this thesis, the developing trends, the basic theory and the multipath channel model of UWB communication are introduced at first. The theory of convolution codes and Viterbi decoding algorithm are discussed next. After that, the thesis lays emphasis on DS-UWB receiver which was based on the method of TURBO iteration. Received signals are created with the aid of software and the whole receiving process is implemented on FPGA. And a storage scheme which can programming the received data into Flash by the SOPC design method is advanced in this design. In addition, in order to coordinate the different clock frequency between Flash and FPGA, an asynchronous FIFO method are designed.which can read and write at the same time as to improve the performance and flexibility of the receiver. LMS algorithm and Viterbi decoding algorithm are used for the received data to enhance receiver performance by adjusting the adaptive weights through the feedback of decoding soft information.