Research Of The Optimization Techniques Of The 128bit High Performance Floating-Point Fused Multiply-Add Unit

Floating-Point Fused Multiply-Add (FMA) Unit is one of the core computing components in high-performance microprocessor, its speed and power consumption have great effect on the performance of entire microprocessor. Along with the increasing requirement of high precision calculation, it becomes significative and valuable in practice to achieve a FMA with high performance and high precision.In this paper, a balanced pipeline architecture of 128 bit FMA is proposed, which has well-proportioned latency at every pipeline stage. In order to enhance the performance and gain more parallelity, some optimization method on the level of algorithm, coding and logic circuit structure are described.This thesis mainly focused on the algorithm, optimization and verification of FMA Unit.1. A 10 stages pipelined architecture of 128bit FMA is proposed, after researching on the algorithm systematically and spliting the pipeline quantificationally.2. To gain more parallelity, some modules on the critical path are optimized. Grouping and parallel design method is employed to the optimization. The details of leading zero anticipator (LZA) have been focused on.3. Based on the two-path adder, the two-path FMA is researched, which has less latency when the FMA processing add instruction.4. Test and verification to the FMA is done. An ideal FMA simulator is implemented to generate the theoretic result. A method for FMA test is introduced,and finally we fulfill the test with special data test, subsection test and test based on exception assorting.The results of logic synthesis show that the frequency of the optimized FMA can reach 465MHz in the smic0.13μm process and 1.075GHZ in the 65nm process, which basically meets the requirements of the high performance computation.