VHDL Implement Of Float-point FFT And The Research On HDL Functional Verification Strategies

With the development of integrated circuit, the Electronic Design Automation (EDA) technology has become an important design method of digital circuit and Digital Signal Processing (DSP) systems. At the same time, with the exponential growth of gates counts and system complexity, functional verification will play a more and more important role.Simulation-based validation and formal verification are two main techniques used to verify correctness. Up to now, the best way of HDL verification is to simulate the HDL design with a massive amount of test pattern because formal verification techniques are frequently intractable for large design. In practice, some well-defined functional coverage metrics are used to perform a quantitative analysis of simulation completeness. Although 100% coverage cannot guarantee a 100% error-free design, it provides a critical standard to measure the completeness of the verification process.This paper firstly presents the design flow of EDA, the importance of functional verification and two correspondent methods, and the construction of testbench. After introducing statement coverage, path coverage, and decision coverage, we pay more attention to du coverage, which is a tractable compromise between the statement coverage metric and the path coverage. Semantic finite state machine (SFSM) coverage is also analyzed. Since Fast Fourier Transform (FFT) is the core technique- of DSP, we finally implement float-point FFT with Very High Speed Hardware Description Language (VHDL) and analyse code coverage of the whole process with our ownbestbench.Radix-2 algorithm and 32-bit single precision format are used in this project and the controller is modeled as a finite state machine. The whole design adopts Xilinx ISE 5.3 series software and advanced structured design mind and it is simulated and verified by ModelSim. Simulation result shows that it takes 875ns to execute the 8-point FFT when main clock frequency is 100MHz. The code coverage of all modules reaches 100% except few exceptional modules, whose code coverage also reaches 90%. Verification result shows that applying VHDL to FFT signal processing can accomplish float-point FFT and the test work is very complete.