Study And Implementation Of BCH Encoding And Decoding In DVB-S2

This thesis focuses on the study of encoding and decoding algorithms, hardware implement and error correcting capability of BCH code, which is used in DVB-S2(Digital Video Broadcasting- Satellite 2).The configurable serial and parallel encoder/decoder used in DVB-S2 has designed and implemented based on the study of encoding and decoding algorithms. Finally, we make an experimental analysis and study of the error correcting capability of BCH and LDPC concatenated code used in DVB-S2. The completed work and production on those three aspects as follows.1. We improved the traditional BCH decoding algorithm based on Berlekamp-Massey iteration. The number of syndrome needs to compute is 2t in traditional iterative decoding algorithm, we has paid more attention to the binary BCH iterative procedure and discovered only 2t-1 syndromes are used in the iteration, the last syndrome is not needed. According to this, the improved decoding algorithm only need to compute 2t-1 syndromes, so simplified the decoding algorithm.2. We designed the serial and parallel encoders of DVB-S2 based on the BCH encoding algorithm. The serial encoder is designed with shift registers, the parallel encoder is consisted of a combinational logic network and remainder registers. On the basis of this, we have a study on the dynamic configurable plan of encoder and put forward the configurable architecture of serial and parallel encoder. These two kinds of encoder have implemented on FPGA, the throughput of 8 bits parallel encoder can achieve 2244Mbps.3. We designed the configurable pipeline architectures of serial and parallel decoder based on the improved decoding algorithm. These architectures take a deep consideration of pipeline and configuration problems caused by more differences between different codes parameters, this enlarged the range of configurable codes parameters. We designed a configurable multiplier architecture, which can be used in different Galoias fields, this save more hardware resources than separately design multiplier in different Galoias fields. Two kinds of decoder have implemented and simulated, the throughput of 8 bits parallel decoder can achieve 1528Mbps.4. We analysed the reseaon of using BCH to concatenate with LDPC in DVB-S2. At first, we simulated and compared the error correcting capability of LDPC and BCH+LDPC in DVB-S2; the concatenated code can deprive 0.5dB coding gain than use LDPC lonely from the result of comparison. Then, we choose a RS code which has the same length and rate as BCH to concatenate with LDPC, the concatenated code of BCH+LDPC can deprive 0.1dB coding gain than RS+LDPC from simulation.