Parametric Design Of BCH/RS Coder/Decoder

In practical application, different communication channels need encoder and decode with different error correcting capability. When choose the encode parameters, it needs corresponding overhead. Generally speaking, we should balance the practical application and operation time when choose code parameters. In high-speed communication system, the contradiction between error correcting capability and operation time is more obvious. As a result, according to the various communications, it should adopt various code parameters.A parametric design of BCH/RS coder and decoder is proposed in this paper, which is implemented in Verilog HDL.The design used BCH/RS encode and decode.BCH is a sort of code with good error correcting capability. It can be easily encoded and decoded. RS is a sort of special code with strong error correcting capability. The parameters of BCH/RS are n, k, t. k is the length of message need to be encoded, n is the length of code after encoding, t is error correcting capability.The scale of chip controllable by limited the maximal parameters, Reconfigured code length and error correcting capability by input signals, BCH coder/decoder have various error correcting capabilities to meet the requirements of different communication system,in order to achieve best data transmission rate. Decoding using the Berlekamp_Massey algorithm and Chien Search.The result of cadence ncverilog simulation confirm that the decoder can correct the errors, and feasible completely. Clock frequency is 500MHZ。...