The LDPC Decoder's Research Based On DTMB Standard

Based on sparse check matrix, Low Density Parity Check (LDPC) Code is a kind of linear block codes, which has the decoding performance of approaching Shannon limit. Its excellent performance promises a good application prospect, for example: LDPC coding scheme was adopted by next satellite digital video broadcast standard. BCH (outer-code) connected LDPC (inner-code) as channel error-correcting codes in the Chinese digital terrestrial media broadcasting(DTMB) system. This paper discusses LDPC decoder around the DTMB.At first, the research situation of LDPC code at home and abroad was analyzed, then, in order to solve the problems of high decoder complexity, the following researches were made in this paper:(1) The LDPC decoding algorithm was studied. Through analysis and comparison with the decoding performance and complexity of the five kinds of decoding algorithm, we could conclude that MS (Min-Sum decoding algorithm) and MSPCF (Min-Sum-Plus-correcting-factor algorithm) hold the lower complexity; and moreover, MSPCF possessed better decoding performance than MS while under the same complexity. Therefore MSPCF algorithm was adopted to design decoder in this paper;(2) This paper focused on the design of decoder structure based on the FPGA realizing of DTMB standard. Through analysis and comparison with the decoding performance and complexity of the three different decoder structures, we could conclude the parallel structure decoding faster but occupying more resources, while the serial structure just the opposite, however, the part-parallel structure compromised their advantages and disadvantages, so the part-parallel structure was employed to design decoder in this paper;(3) Each module of decoder was designed. Through optimization and improvement to the minimum value module from check nodes, the complexity of the decoder was greatly reduced; (4) We established the LPPC decoder simulating system under the Matlab platform, which hold three bit rates in DTMB standards, and analyzed the affections that the number of iterations brought to decoding performance through simulation, finally the number of iterations was determined while the decoder was realized;(5) The 0.6 bit rate LDPC decoder of DTMB standards was realized in FPGA, using Verilog hardware description language to program, then synthesized and simulated in the Quartus II software of Altera Company. At last we got that the decoder occupied 14,618 LEs and the highest work frequency might reach 73.19 MHz.The decoder designed in this paper could satisfy the requirement of DTMB standard, and greatly reduced the complexity of decoder system without losing good decoder performance and decoding speed, which achieved the design goal and laid a good foundation for the application of LDPC decoder.