Design And Research Of ECC In 32-bit EMC

With the development of very large scale integrate circuit and data stored in memory increasing, more and more memory accesses are required. Memory controller is needed to access external memory. As the problem of memory itself or all kinds of noise interference, especially in high speed transmission system, many factors may cause the signal tune over to transmit errors signal. The performance of computer will be affected if we can't correct the errors in time, so is the key data signal that is needed to deal with. It is very important to add error correcting block or error control. In this paper, we design a encoder and decoder block which can have the function of four bits error detection and two bits correction. BCH code has good performance in error correction and has been applied widely in many systems. Binary BCH Error Correction Code is chosen for which is used in memory.The error correcting block in External Memory Controller uses binary BCH code, and the block includes encoder and decoder. In this paper, we research encode algorithm, decode algorithm, implemented in Verilog HDL. And then verify and synthesis them,. About encoder, improvements is made based on serial encode algorithm, we choose combinational logic and the result can be got in one clock period. For decoder block, there are four blocks, and we have done optimization research respectively to meet area and timing request, especially simplified BM iteration calculating error location polynomial. According to actual needs, we choose the BCH(50,32) code, which is the shortened code of BCH(63,45) within GF(26).The end Chapter of the paper concludes the volume, presenting several possible avenues of future research.