Research And Realization Of High-Speed Digital Circuit Silicon Verification

With shrinking channel length of transistors, the actual and simulated circuit behaviors might diverge because of parasitic effects or inaccuracies in the device models. Therefore, it is important to tape-out the critical parts of a new design earlier for silicon verification. In particular, silicon verification is the indispensable process in IP core design.The dissertation presents a complete solution and designs a silicon verification platform for high-speed digital circuit. Scan register chain is used to connect the input-output pins of the circuit under test (CUT). In this way, not only the number of chip pads and the area of chip are reduced, but also controllability or observability for CUT is realized. By separated the transmission of test patterns and responses from the testing process, the at-speed testing without high-speed I/O buffer is implemented. We use a semi-custom method to implement a test circuit and guarantee the solution to have good portability.In this dissertation, silicon verification layout is implemented for a full-custom design CAM. We use the CDA algorithm, which has high fault coverage rate, to test the CAM by a simple testing platform. The test is able to detect stuck-at faults, transition faults, data retention faults, coupling faults, address decoder faults, stuck-open faults, stuck-on faults and so on. The result shows that the solution can greatly reduce the number of chip pads and test cost with a little hardware overhead for the testing circuit.