Study On Interconnect Limits In Deep Sub-Micron IC

As the feature size of integrated circuits (IC) continues to shrink, the operating speed and the integration scale continue to increase, interconnect has increasingly significant effects on performance of IC. Especially in Deep Sub-Micron (DSM) technology, interconnect exhibits transmission line effects and as a result interconnects delay is beyond gate delay and interconnects power is beyond gate power. Therefore, analysis and optimization of interconnects are critical in high-speed IC design. The interconnect limits can be attained via interconnect optimization.The main focus of this paper is study on global interconnects limits, including the limits effects of global interconnects as the technology advances, optimization for global interconnects delay and bandwidth, analysis on global interconnects models, investigation interconnects and CMOS model's effects on performance.(1) Firstly, the paper introduced some concepts related to interconnect. Also interconnects limits overview was presented from the perspectives of theory, device and circuit.(2) The main part of the paper is optimization for global interconnect. It elaborated how interconnects width and spacing affect the delay and bandwidth of interconnects. The discussion on optimization with and without buffer insertion was simulated respectively. The simulation results shown that buffer insertion is an effective way to reduce interconnects delay in DSM.(3) Finally, this paper discussed interconnects models, esp. analyzed the difference between interconnects RC and RLC models based on HSPICE software. The condition for using RC model of global interconnects was validated properly and the criteria for selection of interconnects models was proposed. Then the analysis of interconnects and CMOS models'effects on performance was performed. Conclusion: interconnects models have bigger effects on performance than CMOS models.