Digital Communications, Symbol Timing And Viterbi Decoding Algorithm Research And Implementation

This thesis mainly focuses on the design of symbol timing and Viterbi decoding in the digital communication systems. Then, the FPGA-based symbol timing implementation and DSP-based Viterbi decoding implementation are given. These two algorithms are applied to a digital communication modem of a project.At first, several symbol synchronization methods are introduced. Considering thedemands of this project, we introduce another method of symbol synchronization——interpolation. This algorithm is putted forwards by F. M. Gardner for MPSK signals symbol synchronization, including Interpolator, Timing-Error Detector and NCO. To verify these algorithms, we design some test modules for Quartus's simulation. In the end, convolutional encoding and Viterbi decoding are introduced. We research on the Trellis Paths, Metric Update and Traceback in Viterbi decoding. Decoding is realized by DSP chips.Tests show that the performance meets the requirements of the project.