The Architecture Design Of AHB Matrix Bus Based On AMBA2.0

System on Chip(SoC)is widely used in various electronic devices.In order to reduce the risk and speed up the design process,The on-chip bus is generally applied to reuse IP in SoC.which makes the on-chip bus a key factor in determining the performance of the SoC.Due to the rapid growth of the number of master-slave devices on the bus,traditional bus architectures can hardly meet the requirements of high-speed devices for throughput and access delay,which further restricts the performance of SoC systems.In order to solve this problem,a new kind of bus architecture based on the AMBA 2.0 AMBA bus protocol with parallel transmission mechanism——AHB Bus Matrix is designed in Verilog.The centralized arbitration on the host side is changed to the distributed arbitration on the slave side and the functional modules are divided so that each master and slave device has its own independent interconnect module.On the analysis of AMBA2.0 and AMBA3.0 protocols,the function of AHB bus matrix is defined and the overall architecture and micro-architecture design are completed.Finally,on the basis of completing the code,parameterization is performed.The bus code generation tool is written in Python.The tool can generate the AHB bus matrix code according to different application requirements.In the verification process,firstly,The bus function model is written to establish the verification environment using System Verilog.The single read/write function,incremental read/write function and wrapper read/write function are verified via functional simulation verification.Afterwards,controlling variate method is applied to compare the bus with the traditional AHB bus.A multi-master parallel access single-slave and multi-master cross-parallel access multi-slave tests are performed.The change of throughput and access time with the increment in the number of master and slave for these two buses are obtained and analyzed.The specific data of the area consumption of each function module of the designed bus in the increase of master-slave devices are obtained using Design Compiler.Through comparison and analysis,compared with the traditional AHB bus,the AHB bus matrix can reduce the bus access latency by 3 times and increase the bus throughput by 8.5 times under the condition of multi-host cross-parallel access multi-slave test.In addition,the bus code generation tool can automatically generate a corresponding 2-layer to 8-layer AHB bus matrix code according to the given number of master/slave and slave address segments,effectively improving design efficiency.