Hardware Design Of Image Information Processor Based On ADSP-TS201

In image processing, communication, radar and other fields of real-time signal processing, real-time image information processing have large amount of data computing and throughput, that need large dynamic range of data and high accuracy. It also demands high-speed I/O of processing unit and communication capabilities of processor interconnections. In order to implement algorithms upgrade, the system requires reconfigurability and expansion, so need to build a general real-time parallel image information processing platform.Based on the study of research at home and abroad, choose the DSP, FPGA chips and CPCI bridge circuit carefully, introduce the"dual FPGA+dual DSP cluster+CPCI"frame of image information processor: choose two clusters of total four ADSP TS201 TigerSHARC DSPs from ADI as the kernel processing unit; select two FPGA chips of XC5VLX110T of Virtex-5 family from Xilinx to perform algorithm processing and interface control, implementing reconfigurable framework, taking full advantage of the TigerSHARC DSP to provide ultra-high processing performance and I/O bandwidth; choose CPCI bus as the communication bridge of the image information processor and the host.In this paper, the image information processor schematic is given. The circuit is based on the 6U PCB. TS201 interconnect with FPGA through the shared bus interface and Linkports. The system has large capacity of DDR and DDR2 SDRAM memorys, includ LVDS, SRIO and SATA high-speed communication interface. This paper analysis the signal integrity problem encountered in the system design. Using Si9000 for PCB design and impedance control, focused on discussing the DDR2 and LVDS routing rules, respectively give the PCB BoardSim simulation using HyperLynx7.7. And the choice of backplane connectors and the distribution of pins are discussed. The PCB design work finally completed.The paper also research in the digital design of the high-speed Linkport interconnection between FPGA and TS201, describe the two independent modules of 4-channel source-synchronous DDR LVDS transmitter and receiver in detail, analysis the dynamic setup/hold timing in the receiver design. The simulation results are also given.