The Design And Implement Of Embedded Video Image Detection System Based On FPGA

Because image detection system can acquire quickly a lot of message and is easy to process automatically,at the same time it is easy to integrate design message and machining control message,so it is applied in many fields of modern automation manufacture,such as product monitor,finished product inspection and quality control. In today's industrial applications,image detection system is called upon to tend to be smaller(embedded),at the same time,the demand for real-time of the image detection system is more higher.The development of large-scale integration increases the chip integration,which enrichs FPGA's resources suach as the logic elements,embeded memory blocks and so on,and improves FPGA's performance more and more.So FPGA is used in more and more field of embedded system with its low cost,high parallel ability and flexibility,especially in the video image application situation.A detection system dealing with video-image based on FPGA is designed and implemented in the thesis.The embedded video image detection system based on FPGA mainly include three parts,capture and display,image preprocessing and image detection.The hardware logic of the system is designed with Verilog HDL.A video capture and display system who display the man-machine interface while displaying the dynamic video image is built by design of controller of frame buffer in this paper.The design connects and improves the modules of video capture and video display designed by the two partners.Arming at the FPGA's speciality of good at calculating a large numbers of data parallelly and taking the character image detection as a target,the algorithm hardware circuit of image process suit for the FPGA realization is designed. The five levels pipeline Structure of multifilter in the stage of character image filting is designed,and five kinds of calculation of five filter can be finished in one calculation time,impoving the process speed greatly.In the stage of binary,the threshold is caculated with the Histogram which is easy to realized on hardware.And the error of threshold is avoided by computing the three peak values of the Histogram. In the stage of character partition,the projection is used to divide up the character. The essence fo projection is to calculate the amout of pixel.This method is faster with hareware realization and only need a little resource.In the stage of feature extraction, the 13-point method that is statistical,local-feature-accroding,good adaptablity and easy to realized on hardware is used to extract the features.After the design of hardware,the character detection is done with the module match designed with software,and the results is displayed through the man-machine interface.The functions of hardware and software are divided through SOPC to give full play to the hardware and software features of their own and realize the co-operation of hardware and software to improve the performance of the system.Dsign the algorithms suit for FPGA realization,and overcome the weaknesses that the hardware is difficult to used to realize complex algorithms.Give full play to the characteristics of power parallel data processing of FPGA,so that the image detection system has a higher performance of real-time.Giving full play to the characteristics of the FPGA design flexibility,one only need to change the parameters for differcent detection requirements.The system test results indicate that the real-time video collection and display system can work steadily,and the video character image detection system realized based on the video collection and display system can detect the character accurately。The system has a high performance of real-time and the resource consuming is little.