Design And Implementation Of Nios Ⅱ-based Video Capturing System

With the development of microelectronics and integrated circuit manufacturing technology,the ever-changing technological society,video capture system has been widely used in daily life, industrial production and other fields, which has broad application prospect and research value.Improved integration of video capture system,the rapid development of FPGA provides a new idea and method using FPGA design video capture system has good scalability and sexual stable hardware structure.There are a variety of techniques in the video capture system, such as available microcontroller to control the entire system, but in the application process, the microcontroller can only be applied to general monitoring sites, larger premises in the amount of data, single-chip datathe processing power is not enough, there is the entire system volume is too large, the high cost of maintenance is very inconvenient universal problem.Due to the continuous development of the system on a chip,the superior performance of the Nios Ⅱ processor plays an increasingly important role in the SOPC system. Developers are able to increase the integration of the system by integrating traditional interface within the FPGA. to do so does not affect the performance of the system at the same time greatly shorten the development cycle of the system,This paper studies a video capture programs.The paper introduces the basis of the research SOPC technology and Nios Ⅱ soft-core processor.Then the video image acquisition system design based on Altera’s Cyclone Ⅱ FPGA family.Using FPGA as the main processor,combined with Nios Ⅱ soft-core processor the SOPC system designed image acquisition system of the latest application trends.In the video image signal processing stage,the image processing algorithms mapped to the selected hardware structure,and thus the inherent parallelism and image processing operation using the FPGA logic parallel nature of many image processing algorithms significantly accelerated.Main comp leted the following work: 1、Own design scheme is put forward. This topic adopts FPGA as the system core device, using SOPC technology, combined with the Nios Ⅱ CPU soft core, realize the system’s hardware and software collaborative design, not only to achieve the high performance image processing functions, and reduce the volume of the system, has the very big superiority;2、The video acquisition IP core controller was wrote in the Quartus Ⅱ environment.First of all, through the use of the hardware language to simulate the bus timing to implement the initial configuration of the cameras, then data will be stored into SDRAM which was collected by FIFO buffer;3、We studied seriously the working principle of the video decoding chip named SAA7113,complete the configuration of the chip, and complete the design of the video capture module via the I2C bus. SDRAM for digital image storage principle, to complete the design of the image storage module;4、Nios Ⅱ CPU call the data in the SDRAM into the FIFO buffer, the data is read out and display output through VGA port using the timing control module.