Research On High-bandwidth Data Bus Interface Of Network Processor

With the development of network and communication technology, the transmission rate and structural complexity of Internet based on routing technology have greatly increased. Network Processor is one of the core of routing structure and its data bus interface is the key module of Network Processor for exchanging data with MAC devices. The interface performance makes an important role on whether Network Processor can forward packets with line-speed efficiently.This paper puts forward a scheme of data bus interface module based on the structure of Network Processor and routing technology. The data bus interface achieves data receiving and transmitting with the method of state machine. There are two FIFOs used as data buffer units, and the arbiter unit distributes the bus ownership. They ensure that as long as receive or transmit request on the bus, the data bus interface can work automatically. It accomplishes the data exchange between the Internet Layer and the Network Interface Layer efficiently.The thesis finished the whole structural design and hardware language description, and the module-level and system-level functional simulations are made. The bus interface is able to transfer data being up to 64-bit, can exchange data with high-bandwidth of 6.6Gpbs, It supports multi-modes and multi-NPs interconnect , with better flexibility.