On-chip Micro-structure Of The Network Routing Node And Reconfigurable To Achieve

With the development of Deep SubMicron technology, more and more processors will be integrated on a chip. Traditional communicate mode with bus will gradually can not satisfy the requments of data exchange between different processors. As a key technology used in processor systems, Network on Chip (NOC) is to become one of the most important methods to solve the commucication bottleneck problem in complex multiple processor systems. Along with the development of technology, NOC will take the place of the traditional Bus technology. It will become the focus and a new technology in the related fields. As the most important data exchange unit, the router is of vital importance for the performance of NOC.Based on the previous researches, in this paper, the related technologies of NOC are analyzed in details,especially the router. The main results are as follows:1. The research of the microarchitecture of NOC router. Based on the research of router's architecture, we design and implement thtree kinds of NOC router, Input Queuing, combined Virtural Output Queuing (VOQ) with Output Queuing, and customized arbitral priority router.2. To propose and design a dual-mode NOC communication structure. This dual-mode NOC communication structure combines circuit swithing with packet swithing. It is implemented with 4×4 Mesh topology.3. The reserearch of Dynamic Patial Reconfiguration. We use the EAPR design flow; implement the Dynamic Patial Reconfiguration on Xilinx's FPGA.