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Research On High Performance Data Exchange Bus Based On Multi-core Packet Processor

Posted on:2012-08-02Degree:MasterType:Thesis
Country:ChinaCandidate:J Y ChenFull Text:PDF
GTID:2178330332987457Subject:Microelectronics and Solid State Electronics
Abstract/Summary:PDF Full Text Request
With the development of Internet and microelectronic technology, network processor, as the core equipment of modem network system, is developing toward the direction of MPSoC ( Multi-Processor System On a Chip). Because of its flexibility and high efficiency of the parallel processing mechanism for multiple tasks, programmable and multithreading data processing unit will get strong data processing ability when it's confronted with various Internet protocol and fast increasing network bandwidth. As the key junction for data exchanging in network processor, data exchange bus establishing the data channels and control channels between Fast Bus Interface unit and multi-core processing unit as well as SDRAM unit, it's one of the key units for performance of network processor. It's important for high performance network processor that how to design and implement a high speed Data Exchange Bus.Key technologies of Data Exchange Bus aiming at multithreading packet processing unit are analyzed and researched in this paper. With a parallel structure of push and pull, Data Exchange Bus complete the data and control information transferring in the way of receiving and executing reference instructions of packet processing unit and DMA requests of SDRAM unit; Interface resources asynchronously accessed and thread waked up by signal events mechanism as well as high efficient DMA transfer technology are used for hiding the access latency of Fast Bus Interface resources; Upon classifying and buffering the transfer requests and instructions, and assigning reasonable priorities for each buffer, the bandwidth of data exchange bus is fully used; pipeline structure controlled by transfer command improves the executing efficiency of transfer tasks.Detailed design and RTL level description of data exchange bus are completed in this paper, and the functional and FPGA verification are also accomplished. The available theory bandwidth of data exchange bus attains to 3.41 Gbps and with the statistical bandwidth 2.56 Gbps upon the performance evaluation under a driving frequency 200MHz.
Keywords/Search Tags:Data Exchange Bus MPSoC, Network Processor, Multithreading, Data Channel
PDF Full Text Request
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