Design Of High Speed Data Exchange For Radar Signal Processor

With the rapid development of radar technology,the requirements for the data transmission rate and data processing capabilities of the radar signal processor system are getting higher and higher,and the radar system is required to have higher real-time,inheritance and scalability.Most of the existing radar signal processors use multiple FPGA+DSP device architectures to realize radar system data exchange and related algorithms,which makes the data flow between each device more complicated.Higher transmission rate requirements;The data being processed tends to be diverse.In this paper,the high-speed data exchange of radar signal processor is taken as the main research content.Combining with the development status of radar signal processor,a high-speed data exchange plug-in applied in radar processor is designed and implemented using FPGA,which not only meets the data exchange requirements of all kinds of devices inside modern signal processor,but also improves the flexibility and inheritability of radar system design and reduces the workload of radar designers.The main work contents of this paper are as follows:Firstly,according to the performance requirements of radar signal processor,the theory of radar signal processor,high-speed data exchange,AXI bus and high-speed serial transceiver is introduced,and the design scheme of switching plug-in is determined based on their respective characteristics.According to the system design scheme,the overall structure of the hardware circuit of the switching plug-in is determined,and the selection of core components,the circuit schematic design of each module,the hardware PCB design and the power supply test of the hardware circuit board card are completed in turn.In the layout and wiring of high-speed devices such as DDR3 and GTX transceivers,the corresponding design principles should be observed.Through the test of hardware circuit,the normal operation of board card hardware is guaranteed.Secondly,according to the functional requirements of the system scheme design,this paper divides the logic functions that the high-speed switching plug-in needs to complete,and mainly completes the logic design of clock chip configuration,the logic design of RapidIO data transmission,the logic design of DDR3 cache and the logic design of data exchange.By writing RapidIO data transceiver logic and using AXI Data Mover to realize DDR3 memory FIFO,the design foundation of data exchange logic is provided.The design of data exchange logic in this paper is realized by two methods: one is the data exchange method realized by using AXI Stream Interconnect,the other is the high-speed data exchange method realized by using the mainstream Crossbar exchange structure and various scheduling algorithms combined with the characteristics of AXI4 Stream bus.The second switching logic solves the HOL queue blocking problem and the data exchange capacity decline problem under output conflict.It has a variety of switching scheduling algorithms to choose from,and has higher performance and wider application scenarios than the first switching structure.Finally,the hardware environment of the whole radar system is built,and the functional logic on the switching plug-in is verified by Vivado software.The whole imaging radar system completes the functions of real-time imaging,echo recording and functional self-checking,which fully verifies the logic function of the switching plug-in.The resource occupancy and timing performance parameters of the switching plug-in are given.The test results show that the high-speed data exchange plug-in of radar signal processor designed in this paper can work stably,meet the various indicators of the radar system,reduce the complexity of the radar system and improve the expansibility of the radar signal processor.