Study On The Structure Model Of Strained CMOS Device

Strained silicon technology enhances the carrier mobility in bulk Si CMOS by introducing tensile or compressive stress into Si device. In addition, based on the process of Bulk Si CMOS, Strained silicon technology needs no complicated methods in process line, thus being widely applied as a cheap and efficient methodology, and maintaining the continuation of Moore's Law.This thesis designed a novel structure modle of strained CMOS device which is integrated by strained silicon surface channel NMOSFT and strained silicon vertical channel PMOSFET. This CMOS structure not only used the novel technology, but also fited and promoted the process line of our country, which is advance and economical with a grate future. This novel strained CMOS structure is a creative design and hasn't been reported previously.For the sake of simulating and modeling the novel strained CMOS, the main device physical parameters such as threshold voltage and effective carrier mobility are established. After that, the integrated strained CMOS was simulated by Medici to research on the DC steady and AC small signal characteristics and major structure parameters of device.The result from the simulation demonstrated that this novel strained CMOS structure is well designed and will have a promising future in the application field.