Research And Design In Synchronization Modules For DTTB Demodulator

OFDM modulation technique is used in Terrestrial digital broadcasting demodulator to improve the spectrum efficiency and effective against multipath fading. OFDM system is very sensitive to timing error, carrier frequency offset and sampling frequency offset which must be estimated and compensated in order to receive the correct data that process is called synchronization, synchronization module directly impacts the performance of the receiver.This work investigates the principle of OFDM and DTTB system and focus on the design of synchronous module and propose the synchronization system and circuit the for pilot-based (DVB-T) and time-domain training sequence based(DTMB). Points out that there are several standards in the digital TV terrestrial standard, the author proposes a novel mode dual(TDS-OFDM&DVB-T) demodulator synchronization solution with high performance and low hardware consumption.Main achievement was as follows:(1) Based on the investigation of the digital TV technology development, the DVB-T and DTMB modulator and their demodulator architecture, wireless channel model, requirement to synchronization and their effect have been detailly discussed. Novel dual-mode architecture with lower complexity and lower power has been proposed.(2) Analysis the characteristics of PN sequences in DTMB system, design a variable length correlator of the time-domain. By changing the correlation length, not only reduce the resources costs, and also expand the frequency estimation range. In the sliding correlation, a sliding window is designed to open from time to time,which can reduce power consumption.(3) The synchronization algorithms and circuits of DVB-T and DTMB receivers, which include symbol offset, carrier frequency offset and sampling frequency, have been optimized and realized. After the analysis of existed ML algorithm, a low complexity sign ML detector for OFDM systems has been proposed that 88% chip area a have been saved.(4) In this paper, a dual-mode synchronous demodulator module is realized, and take fully into account the sharing of resources that reducing resource consumption. Using Verilog HDL language to describe the entire design and Top-Down design methodology. The test platerform for digital TV demodulator based on FPGA has been designed. Parts of the designed circuits have been embedded into the FPGA, and their function and some performace been tested by using the TS signals generated by SFU of R&S. The results show that the proposed algorithms and circuits can meet the requirement of the specification.