IP Soft Core Design Of Full Digital Three-Phase Spwm Signal Generation System

According to the requirement of the VLSI and the wide application of power electronics, IP soft core of SPWM generation system is designed. And it can be widely applied in system level chip design.Firstly, the necessity of designing the full digital three-phase SPWM signal generation system is discussed by analyzing the actuality of the IC development and the application of the PWM technology in power electronics.Secondly, the principle and Direct Digital Frequency Synthesis (DDS) is analyzed deeply.Thirdly, the whole system is designed according to the design flow. The main process includes following: system design, module design and function stimulation. The whole system is divided into several modules and each module is connected by signals, which based on the arithmetic of SPWM and the requirement of design. The module design is to design inner circuit structure of each module and uses Verilog language to code the synthesizable and reusable code. The functional stimulation uses the NC-Verilog of Cadence. First, each module is simulated. Then, after the right result comes out, the code of each module is assembled to form the code of whole system. Last, the simulation signal is applied on outer port to simulate the whole system. Together, in this part coding the reusable and synthesizable code was deeply discussed.Lastly, FPGA is used to test the function of the system. The FPGA chip used isXC2S50PQ208 of Xilinx. The configure file is downloaded into the FPGA chip according to the FPGA design flow. Also a test system is set up, and the work status of the system is controlled by single chip to download the data of initial registers and control registesr. And the logical analyzer is used to sampling the output signals. The results of function test show that the design accomplished the requirements perfectly.