The Research And Implementation Test Generation Based On Genetic Algorithm Using FPGA

With the development of the design for digital integrated circuits and the technique of craft, the scale of integrated circuits become more and more large, the structure becomes increasingly complex, the test for integrated circuits is becoming increasingly difficult. The Design-for-Testability(DFT) technique is a good method to solve test problem. Build-In Self-Test(BIST) is a kind of most important and widely used DFT technologies. A proper Test Patten Generator (TPG) is the essential part in any BIST technique.On the basis of introducing the principle of digital integrated circuits testing and genetic algorithm(GA), this thesis focuses on an automatic test generate method using test vectors applied by Circuit-under-Test(CUT) automatically to address some current technical problems. To find a approximately optimal feedback combination, the use of GA doing adaptive search, but using software to achieve this complex issue is always restricted by computer system which is essentially serial at speed. Therefore, it has a great meaning for hardware implementation. The main accomplished tasks of this thesis including the following parts:(1) The current commonly used TPG is researched in detail, an analysis of the advantages and disadvantages of these techniques. At the same time, FPGA design methods and characteristics are depth of discussion.(2) The basic theory of genetic algorithm is studied deeply, a kind of hardware circuit architecture about test generation method based on GA using FPGA is proposed. From several aspects, such as system architecture design, genetic operator realization, the thesis details the system design thinking and realization process. And the complex modules are optimized, these methods of optimization includes: pipeline technique is used to raising the clock frequency, selection module and fitness module parallel technique is introduced, the use of dual-port memory module to increase the speed of data reading and writing.(3) The basic theory of fault simulation is studied deeply, combined with FPGA owned characteristics, using fault injection circuits and dual-port memory storing fault list, a fault simulator is designed and implemented, which has fault selection and fault delete functions. (4) The whole system is simulated and verified in QuartusII and Modelsim environment. The hardware system processor has been implemented in Altera FPGA Stratix EP1S40F1020C5. The VHDL is used to describe the whole system. The results show that: test generation method based on GA and fault simulator using FPGA can operate under higher frequency. The design achieved a well utilization of resources and speed of state and can efficiently reduce the run time, the expectant design aim is fulfilled.