Design Of Digital Optical Terminal Based On LVDS Technology

Along with the rapid development of China's modernization process and the constant emergencies occur, industrial and mining enterprises, the city traffic, highway and railway electrification, urban public safety and emergency systems, emergencies and other aspects of the surveillance management system have gained more and more attention. This paper considers the transmission of uncompressed tetra-channel digital video, tetra-channel bidirectional audio and dual-channel bidirectional data using a single optical fiber. The hardware design includes video, audio, data and LVDS serializer based on FPGA. The software design implements TDM and signal denoising using VHDL language. The whole set of design of digital optical terminal employing LVDS technology has been achieved.1 Hardware design includes the design of video module, audio module, data module and multiplexer module.1.1 Video module, the sending end collect the image through the external monitor, and goes through analog signal amplification, analog-to-digital conversion. At the very end, it is transformed into digital video which the FPGA can handle. At the receiving end, after frequency distribution, digital-analog conversion and amplification are performed by tetra-channel digital video, then analog video signal was transferred to the monitor.1.2 Audio module, the sending end pickup external sound, analog signal amplification and analog-to-digital conversion are then performed to get the digital audio signal. During the design process, in order to conserve bandwidth, the three clock signal in audio processing module MCLK, LRCK, SCLK do not transmit through the fiber-optic, instead of receiving end of the received signal divide frequency. Audio module receiving end, digital audio signals goes through digital-to-analog converter and amplification, analog audio signal is obtained and sent to the monitor.1.3 Data modules, data signal of the RS232 level are transformed to the TTL level at the sending end. The opposite process is performed at the receiving side. This completed the two computers through fiber optic cable communications functions.1.4 Multiplexer module, at the sending end, FPGA and the LVDS equipment let the tetra-channel video signals, audio signals and dual-channel data signals to be transformed to high-speed TDM and high-speed digital signal and transferred through optical fiber switch to the other side of cable. And let reverse deliver high speed digital signal including tetra-channel receive audio signal and dual-channel receive data signal decompose. Multiplexer module receiving end let high speed digital signal (including tetra-channel video signal, tetra-channel audio signal and dual-channel data signal) switch to low speed decompose connect and decompose according to the TDM method. And let reverse transmission tetra-channel dispatch audio signal and dual-channel dispatch data signal TDM and high speed connect, in order to get one-channel high speed digital signal and transform to the other end of optical fiber. And reverse transmission received contains four dual-channel audio signals and data signals received by the high-speed digital signal series of solutions, and in accordance with time-division multiplexing tap method. The receiver end of multiplexer module to complete the function and the sending end the contrary, it is being transmitted over high-speed digital signals (including the tetra-channel video signal, tetra-channel audio signals and data signals) to low-speed SerDes and in accordance with the method of time-division multiplexing demultiplexer; and to reverse the tetra-channel transmission of audio signals and sending dual-channel data transmission and high-speed time-division multiplexing signals to be equivalent to the way string of high-speed digital signal through the cable to the other end of transmission.2 Software design include video signal, audio signal, data signal, lamp, reverse transform audio and data signal and 8B/10B code design. 2.1 The sending end of the video signal let analog-to-digital conversion of four 8bit video signal sent to the FPGA in the video DX_REG register (X respected ABCD), in order to prevent the adoption of external noise into the video capture video register, in the absence of video transmission, register will be "00000000". The receiving end tetra-channel tap video signal read out from the register after FPGA second separate, then sent to the corresponding digital-to-analog chips to transform.2.2 The sending end of the audio signal sent audio signals to the FPGA audio registers, then multiplexed. And one-third of the system clock frequency of CLK, the frequency has been sent to the audio processing chip MCLK, through audio analog-to-digital conversion chip internal functions output SCLK and LRCK, sent to FPGA. In order to save transmission bandwidth, the three clock signals of audio do not transmit through the optical fiber, but the acceptance by the other side of the signal frequency RCLK frequency; FPGA receiver will receive the second tap of the four audio signals read from the register that is sent to the corresponding digital-to-analog converter chip, for digital-to-analog conversion. The frequency of MCLK is signal reception and one-third of the frequency of RCLK frequency; The SCLK is a quarter of MCLK frequency; the LRCK is MCLK 1/256 frequency. Sent them all to the audio digital-to-analog converter chip.2.3 The sending end of the data signal send data signal to the FPGA register. The receiving end, send data signal to the data processing module after FPGA handled. Program is designed to focus on the inspection of data signals to examine tremble and eliminate shake. This paper designs a judgment method for the elimination of the data signal jitter phenomena. Method is that all the three consecutive data signals to determine, if the number of high-level more than low-level, then output high-level, otherwise output low-level. It is very obvious effect of experimental verification, and a very good method to eliminate the jitter phenomenon.2.4 Multiplexer is the idea of using time-division multiplexing, three types of signals transmitted in two slots. The first time slot transmits 1, 2-channel of video signals and the entire tetra-channel audio signal; the second time slot transmits 3, 4-channel of video signals and the entire dual-channel data signals. In order to distinguish time slot, the paper introduces the bit determination OUTDATA_REGP, at the first slot of sending end marked 11, at the second slot of sending end marked 00. Determine receiving slot at the receiving end, thereby determining the transmission signal.2.5 Lamp control, the sending end of the video signal based on analog-to-digital converter output CLAMP pin to control the sending end of video signal lamp. In the absence of signal transmission, all the data registers install 0. In the same way, other signal lamp detect corresponding register to determine whether there is high signal, in order to insure whether the lamp is on.2.6 8B/10B codec is designed to deal with reverse transmission of audio and data signals. It composed of 3B/4B codec and 5B/6B codec. 8B/10B encode introduce Disparity, so that 0 and 1 are balanced in the data flow, and introduce Run Disparity (RD), to undertake units of bytes of data flow encoding. That is, RD is the encoded data flow of Disparity statistics. Because disparity for the neutral as a result of the value can not satisfy all the requirements of 8bit data, they need access Disparity value for the±2, so that every 8bit encoding data corresponding to the two 10bit values, to ensure transmission to fit in with DC-balanced. Programming based on RD encoding chooses suitable 10bit value to transmit. 8B/10B decoder according to coding rules, design a functional of choose 1 in 2 elections. That is, when everyone turns up in two 10bit data that we can output corresponding 8bit value to complete coding function.