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Function Verification Of Video Signal Process Chip Based On SVA

Posted on:2008-10-06Degree:MasterType:Thesis
Country:ChinaCandidate:S C DingFull Text:PDF
GTID:2178360245492956Subject:Microelectronics and Solid State Electronics
Abstract/Summary:PDF Full Text Request
Function verification has become the largest bottleneck in the design process as the IC technology develops and the scale of SoC circuits grows. It takes 50% ~ 70% time of the design cycle which will be even more as the scale of design grows. The usual method of function verification is simulation-based dynamic verification. However, the traditional simulation-based verification suffers from some obvious deficiencies: lower observability and controllability, difficult debugging, lower reusability of verification environment and lower automation of simulation process.In this thesis, an assertion-based-verificaiton method based on SystemVerilog assertion (SVA) is discussed. According to the features of SVA, a layer-based testbench is established and the process of the verification is discussed. Refers to the design and implement specifications of the video signal process chip, we establish a layer-based verification plan and carry out the verification (limit to length, only the Data Access and Center Controll Systems are introduced). For each layer, we develop SVA checkers, select testcases, adopt both directed and constraint directed stimulus, make use of information collected by SVA to guide the stimulus generations.The experimental results show that, the SVA-based-verification can make a good join of the three elements in verification environment (sitimulus generation, check mechanism and function coverage analysis), bring full advantage of each element into play, optimize the verification environment, improve the observability and controllability, reduce the debugging, increase the reusability of testbench and the automation of simulation, improve verification quality and efficiency. As a result, it can effectly cut short the develop cycle, increase the confidence of the design and guarantee the successful tape-out.This thesis is from Tianjin Municipal Science and Technology Development Project"The Development of Video Signal Process Chip". Now, the project has been checked and accepted by Tianjin Municipal Science and Technology Commission.
Keywords/Search Tags:Function Verification, SVA, Constraint-Random-Stimulus, Coverage-Driven, Video Signal Process Chip
PDF Full Text Request
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