Optimized Design And Implementation Of A Radar Signal Processor

This paper is based on the optimization of data processor of some guidance radar. It is introduced the design and implementation of the software and hardware of the coherent-on-receive process(CORP) and moving target indicator(MTI) system, which includes the debugging and optimizing processes of both software and hardware parts. It is firstly reviewed in the paper several methods of signal data processing, such as Digital Stable Unit(DSU), pulse repetition frequency(PRF) staggering, moving target indicator(MTI) and etc. Then simulations of all these methods are implemented. Thereafter, it is introduced the structure of the radar signal processor, the optimized design of the system and its main function assignment. In the end, it is specifically discussed the implementation of all parts consisting of radar signal processor, the optimized design of ADSP TS201S memory. The radar incorporates techniques such as CORP, PRF staggering and anti-jamming. The system works on the platform which uses StratixII chips of ALTERA and ADSP TS201S with high performance. The soft core of the system is designed with VHDL, assemble and C. The result shows that coding with optimized memory design could highly improve the efficiency of the system and that the optimized system could advance the real-time property within the limited system resource.