Design On Embedded Radar Video Information Acquisition System

With the development of radar and embedded system technology, modern radar is tending to high definition, more powerful and good real-time. As the subsystem of radar system, designing high-powered acquisition system of radar digital video information is more significant.In this thesis, radar video information acquisition system has realized. In which, a shared Dual-Port RAM structure based FPGA has designed, as buffer and logical interface between ARM and FPGA. It simplifies the procedure that the radar video data are sent from FPGA to ARM, meanwhile, this system adopts FPGA-based hardware circuit to realize coordinate conversion. Such these designs improve the overall system efficiently. The system used embedded Linux as operating system. It's an effective guarantee of real-time, reliability and scalability. The system has also realized Dual-Port RAM driver based on memory mapping and asynchronous I/O mechanism, laying solid foundation for the development of application. In order to facilitate maintenance and communication with other subsystems in the future, this thesis introduces a design of remote communication software based on the TCP/IP protocol, using double-buffer queue, it obviously avoids the deadline in communication and applies in reliable and effective connection.The test demonstrates that the radar video acquisition system enhances obviously in acquired velocity and reponse time, achieving the expected demand, and this system is lower power, lower price, higher acquired velocity and better expansibility which are less available for the conventional radar system.