The Realization Of Iterative Message Passing Algorithm For Fast Acquisition Based On FPGA

Oceanic wireless navigation systems use earth signals for navigantion and positioning, but in the environment of oceanic wireless electric wave propagation, there is serious sky wave interfere, which may seriously harm to the natual work of receivers. To eliminate the sky wave interfere, a fast synchronization algorithm which can track the sky wave in real time is required. In this situation, a fast acquisition algorithm based on IMPA(iterative message passing algorithm) was proposed in this paper.This method roots in the quickly developed iterative decoding algorithm which belongs to the coding theories. The principle of IMPA, including the factor graph theories and the message passing theories based on the factor graphs was analyzed in detail in this paper, which is the basis of IMPA. On the foundation of the IMPA, to realize the acquisition of PN code, repeating the iterative operation of the demodulated chip level channel signals on the factor graphs which indicates the local constraint relationship is required, finally the maximum posterior estimate would be found. The realization scheme and material operation steps of the fast PN code acquisition method based on IMPA was given in this paper, also the simulation and analysis of the algorithm's performance was done. The results of the simulation and analysis indicates that the fast PN code acquisition method based on IMPA can perfectly do the mission of fast capturing the sky wave interferential signals.The mission of realizing the fast PN code acquisition algorithm on FPGA was done in this paper. This algorithm requires huge account operations and resources, its being capable of parallel processing make it be suitable for realizing on FPGA. The realization of the method was based on Verilog HDL, the coding style used Altera's standards, popular tools of synthesis, simulation and design were used in the work. This paper divided the whole algorithm into three modules to be realized respectively, technical realization scheme and simulation results of each module were given in this paper, the realization method of the whole design was also presented. After the timing simulation, debugging on board was finished, which proved that the algorithm is realizable on hardware and indicated that the algorithm is effective and usable.