The Research And Implementation Of LDPC Codes Decoding Algorithm Based On Factor Graphs And FPGA

Low-Density Parity-Check codes has attracted much attention from researchers due to its outstanding error correcting ability and parallel decoding after its rediscovery in 1996, and has been adopted by many middle and long distance wireless data transmission standards, such as DVB-T2, IEEE 802.11, IEEE802.16 and etc. Because of the high computing and implementation complexity, application occasions of LDPC codes are limited to wireless communication devices with large scale, like satellite, base stations. However, on low power consumption mobile devices applications, LDPC codes meet great obstacles.This paper proposes a simplified initialization decoding algorithm based on LDPC decoding procedure on factor graphs and features of FPGA platform, as well as the corresponding decoder design scheme. The main content of this paper is as follow:In the aspect of LDPC decoding algorithm, the basic approaches and concepts of Belief Propagation algorithm, Min-Sum algorithm and factor graphs are first introduced. And after researching the procedure of LDPC decoding on factor graphs, that the initialization step is finished by variable nodes in factor graphs is discovered, which the proposal of Simplified Initialization Belief Propagation(SI-BP) algorithm is based on. With the improvements on SI-BP algorithm, the Simplified Initialization Min-Sum(SI-MS) algorithm is proposed, which is more suitable for the implementation of LDPC decoder on FPGA.In the aspect of decoder designing, a multi-length parallel decoder design scheme is proposed for rate 0.4 LDPC codes from CCSDS 131.1-O-1 standard. Constructing method of each part in decoder is illustrated specifically, besides variable nodes update model, check nodes update model, addressing model and etc., especially ports design, working states and timing sequences of each model. Based on the decoder design scheme, a(2560, 1024) LDPC decoder is implemented on Xilinx XC4VSX35 FPGA platform, 7.48 d B coding gain, 541 kbps information transmitting speed and 1.35 Mbps symbol transmitting speed is achieved while the bit error rate(BER) is 1e-5.