Research On Adpll-Basedtime Digital Converter

TDC (Time Digital Converter, TDC) is the common measurement of the time circuit, its main function is to calculate the main reference signal to the incident and the time interval between pulses, and digital output.The interval of time will directly translate into high-precision digital value and achieve digital signals. TDC has been widely used in electronics, often used in the field of electronic testing (for example: DPLL,ADPLL)to improve their test devices and signal characteristics of the time. In recent years, the TDC is most concerned about the use of high-speed digital CMOS circuit structure, mainly due to be test signals to achieve a higher accuracy of the time. TDC on the accuracy of research will be beneficial to the application of TDC and quality assurance.This paper aims to study the time-to-digital converter's accuracy, according to an all-digital phase locked loop circuit in time-to-digital converter on the structure and performance, the TDC design method. Using the EDA software to draw circuit diagrams,and the fastest logic-level regenerative timing algorithm through the VHDL language of the TDC circuit encoded signal. Finally, design the test circuit and get the simulation results obtained to TDC for the accuracy of the measurement accuracy. The main work and achievements are as follows:1. Design of the TDC module circuit; Using PSPICE software tools, through the introduction of the basic flip-flops, amplifiers, and other devices, design a top-level model of TDC, make the foundation for the further analysis of the accuracy. Make the circuit simulation, analysis of the temperature of the current and voltage digital signal transmission delay.2. Study on the structure of the TDC core; Using the HSPICE software tools, through the gate circuit to analyze the flip-flop by programming the devices to achieve each of the gate leakage source, as well as the length of the line, and other parameters of the underlying design of the main devices of different transmission capability. Get the specific impact to the delay from the voltage-current and the the bureau of the department of the device line to determine the priority level, measured the time delay under the CMOS linear trend.3. According to the TDC's performance in ADPLL, study in-depth of the strengths and weaknesses of the existing TDC on the basis of a self-correcting algorithm. Based on the establishment of the correct analysis of the program,through improve the fixed vector for TDC simulation, prove the rationality and feasibility of the research.4. This article on the work of top-down analysis in detail, the basis for software and hardware development process, the introduction of a more level. In this paper, sum at the same time the research analysis and prospects in the future.