Research On Strained MOS Devices Characteristics

Strained MOS device is introducing strain into Silicon-based MOS device manufacturing process. Making use of the lattice constant of Si and SiGe, compressive or tensile can be produced, thereby it can enhance the carrier mobility. This makes the performance of MOS device access to a high improvement in the case of its feature size constant. In addition, strained MOS device has the advantages of being compatible with the conventional Si technology and adjustable band structure. Because strained MOS device has many advantages mentioned above, in the case of a slight increase in investment, it would be applied to existing IC production lines, this will not only make a substantial increase in chip performance, but also greatly extend the use life of the costly IC production line. Therefore, strained MOS device has a good prospect.In addition, due to hole mobility is lower than electron mobility in the crystal Si, so the current drive capability and speed of PMOS are lower than NMOS. Therefore, the performance of Si-based CMOS circuits heavily influenced by the constraints of PMOS devices. In the CMOS integrated circuit design, in order to make the performance of PMOS and NMOS match, the layout area of PMOS is usually 2 to 3 times larger than NMOS, this will lead to the integration and the speed reduced, the power consumption will increase too. The strained SiGe quantum well channel PMOS can effectively improve the hole mobility and enhance driving capability. Thus, in order to ensure the consistent drive capability, the strained SiGe quantum well channel PMOS which has relatively small width to length ratio, can be used in CMOS circuits. This will not only reduce the chip area, but also ensure the symmetry of CMOS. And the performance of the circuits will be improved.The content of this paper is research on strained MOS device characteristics and the following research work have been done: The research and development status of strained MOS device in domestic and foreign were analyzed, the problems faced were illustrated; Started from the basic physical properties of the material, this paper studied the lattice structure and the band structure of strained Si and strained SiGe; The advantages of strained MOS devices were analyzed, the importance of the research on strained MOS device was explained; The Synopsys'device simulation software—ISETCAD was learned, the method and the models used for device simulation were studied in this paper. The device structures of the strained Si surface channel NMOS and the strained SiGe quantum well channel PMOS were designed. In order to optimize the device structures and to enhance the device performance, the main electrical characteristics of the designed device structures were simulated, such as the DC characteristics, the transconductance and the characteristic frequency, and the main structural parameters impacting on the device performance were studied.