FPGA-based Technology Of Receibing And Processing With High-speed Digitalization

In the system of the Radar passive detecting and electronic reconnaissance,the demand of the bandwidth of the data receiving and the speed of the data transmitting is becoming higher and higher.Nowadays,as the fast development of the ADC,there are many ADCs have applied in the system of electronic and information such as the ADCs of those with 12 differentiating bits and 200 million sampling per second and those with 12 differentiating bits and 400 million sampling per second.And the bandwidth of the data receiving can extend to 200MHz easily.From the market,it is easily to get the ADCs with 8 differentiating bits and 1.5 gigabit sampling per second,even get the higher ones.With respect to the data transmitting,it is common to use USB,PCI,and FPDP protocol,and the pipelining speed of the USB bus can achieve the max speed of 50 million bytes per second on protocol 2.0,the pipelining speed of the PCI bus can achieve the speed from 132MBps to 528MBps by setting the frequency of 33 million or 66 million and bits width of 32 bits or 64 bits.Now,the FPDP protocol's speed is up to 400 MBps.The signal-processing board in my design samples the signal whose instantaneous bandwidth more than 100 MHz with high speed by using the AD9430 which has 12 differentiating bits and 200 million sampling per second,so it gets the data rate of the 400 MBps.After digitalization signal detecting with high efficiency and real time,the board buffers the data separately by using the memory inner the Virtex-ⅡPro XC2VP7 and the DDR SDRAM with the capability of 64 million bytes on the board,so the board has the ability of transmitting the data by selecting the fibre or the Ethernet.The main of my design is to solve the inconsistency between the high speed of the data receiving from the digitalization of the wide band signal and the slow speed of the computer's reading or writing,and is to transmit the data whose peak speed is 400Mbytes/s from the high speed ADC by fibre and gigabit Ethernet.So my design mainly conclude the design of the ADC module with high speed and high precision and application of the signal detecting and the data buffering and data transmitting by fibre and gigabit Ethernet and so on.By measuring in the real environment,the largest width of the pulse to buffer by fibre transmitting is 80 milliseconds,and the largest width of the pulse to buffer by gigabit Ethemet is 400 milliseconds.