Design Of Synchronous Digital MULDEX System Based On FPGA

Digital multiplexing and demultiplexing, an important technique in the network of communication, can improve the transmission efficiency in the way of multiplexing several low speed data flows into a high speed one. In addition to better design flexibility and save system resource, digital MULDEX system based on the FPGA also make the problem of modifying structure of circuit easier.This paper deals with the implementation and modeling of synchronous digital MULDEX system based on the FPGA. Firstly it presents EDA technology and its development, then describes the theory of synchronous digital MULDEX system. By using top-down design method, a way for designing MULDEX system based on the FPGA is introduced. Not only the design step and idiographic function of synchronous digital multiplexer and synchronous digital demultiplexer is presented, but design idea is also put forward. This paper analyzes the implementation of frame synchronization circuit and DPLL circuit in the bit synchronization ,along with their simulation result in Quartus II which has been explained in detail. The function of the designed MULDEX system can be accomplished that multiplexes four branches of 25Mb/s into one data flow of 100Mb/s and then demultiplexes the data flow into four branches, positive justification used during the course of multiplex. This system features have high reliability and good flexibility.