Design-for-Testability Optimal Strategy And Design-for-Testability Research Based On Network-on-Chip

As the development of IC (Integrate Circuit) manufacturing and the increases of the density and complexity of VLSI circuits, the difficulty of IC testing increases quickly and its cost goes up exponentially. The traditional test method could not meet the present test requirement. In that case, there should be new test ideas and methods to solve this problem. DFT(Design for Testability), a new design method considering the system test problem during IC design period, has appeared. According to testability design criterions and rules of the circuit, design structures and modules are added during design period by DFT to make IC capable of being tested.As the number of Intellectual Property (IP) cores integrated in a single chip is becoming larger, the traditional bus-based interconnection has become more and more localization in many aspects. NoC (Networks-on-Chip) appears to solve communication problems on the chip when the dimension of SoC (System-on-Chip) increases bigger and bigger. Along with the apperence of NoC structure and design method, the density and complexity of NoC far exceed that of SoC. The corresponding test difficulty and cost increase a lot, so that the known DFT should have some reforms to adapt with NoC. Therefore, it is significant to research the DFT technology based on NoC.The thesis has accomplished the design and implementation of DFT strategy in RPR ASIC back-end design. Based on researching requirements of RPR ASIC, the thesis analysises the comprehensive application of various DFT methods, chooses appropriate methods, presents corresponding DFT strategy and optimal solution which is implemented during the process of adding the DFT structure, and then analyzes the result of the strategy.According to a 2-D mesh topology, the thesis researches the DFT design problem of NoC. It presents test access mechanism (TAM) architecture,test flow and the key control module's design strategy of DFT for NoC. TAM architecture of NoC is based on the reuse of the interconnection on the chip. All the test data are transferred and received in the packets form. Compare with the traditional bus-based TAM architecture, its parallelism is improved without idle time of resources. The whole test process is executed under the control of a test control center module.The RPR ASIC has been taped out and passed 863 national program specialists'check. Research on"The Interconnection Networks and Design for Testability of Networks-on-Chip"supported in part by the National Natural Science Foundation of China, has passed the metaphase estimate by the fund program specialists.