The Design Of DVB-S Demodulation System And The Research Of The Key Technology Based On DVB-S2 Demodulation System

Recently, with the continuous development of digital technology, the business of digital video broadcasting has been making great progress. One of the most important ways is satellite digital television broadcasting. DVB-S has been adopted by most country widely. However, the frequency resource is more and more rare, QPSK is faced with challenge for its frequent efficiency is not high. Therefore the DVB standard organization is proposing DVB-S2 standard, which consists of 8PSK modulation and LDPC encode. Comparing with DVB-S, DVB-S2 has many advantages, e.g. the thirty percent increase in channel capacity, the more reliable performance, and the more efficient usage of transponders. The research of demodulation system based on DVB-S2 becomes a very hot research issue.This paper introduces a DVB-S demodulation system design based on the platform of LSI SC2005 according to the research of the key technology about demodulation, such as the DVB-S standard, QPSK demodulation, digitized synchronization technology .The DVB-S demodulation system contains some modules. Hardware design and software design of a few important modules are introduced. The structure and the demodulate process of THOMSON DSF8910 is introduced. A state machine and the drivers of the digital Satellite front-end are designed in this paper. Then the circuit diagram of this module is analyzed.Through analyzing the DVB-S2 demodulation algorithm including carrier recovery and clock timing recovery, an all digital MPSK demodulator suitable to the next generation digital satellite television standard DVB-S2 was proposed. The carrier recovery algorithm consist s of a frequency detector (FD) loop and a modified phase-frequency detector (PFD) loop .The modified Gardner TED algorithm was used in the clock timing recovery loop. Results of analysis and computer simulation were applied to determine the optimal parameter of each loop. This paper introduces a design of the digital demodulation of DVB-S2, and provides detailed explanations on the carrier recovery and clock timing recovery algorithm according to the characteristics of FPGA.