Studies On All Digital Ultra-high Speed MPSK Demodulation Techniques Based On FPGA

As an important component of Satellite engineering, TT&C(Tracking Telemetering and Command) and Communication system is becoming a system with higher speed and being all-digital. This requires the high speed demodulator to be more flexible and robust. In this dissertation, the key techniques including carrier recovery, timing synchronization and equalization are studied and an equalizer is designed and implemented to improve the performance of demodulator.Firstly, carrier recovery technique is studied. On the basis of the former demodulator developed by our lab, analysis is made on the carrier recovery loop and simulation validates the analysis.Secondly, as the key algorithm of timing synchronization, the timing error detection method is studied. After introducing the popular timing error detection algorithm, analysis is made on the classical GTDA algorithm and simulation is done to validate the function of GTDA algorithm. Simulation results show that GTDA algorithm can meet the design requirements of the demodulation system.In order to improve the demodulation performance, adaptive equalization technique should be used to reduce the influence of ISI(inter-symbol interference) when the needed information of practical communication channel can not be fully known. After analyzing many equalization methods and by comparing the performance of different methods, this dissertation designs an adaptive equalizer in order to improve the demodulation performance. Simulation is done to validate the design of equalizer. The entire demodulation system is simulated, synthesized, and downloaded to FPGA for functional verifications.