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Design And Implentation Of An IF Digital Receiver

Posted on:2008-04-02Degree:MasterType:Thesis
Country:ChinaCandidate:B B CuiFull Text:PDF
GTID:2178360245997687Subject:Information and Communication Engineering
Abstract/Summary:PDF Full Text Request
One of the important conceptions of Software Radio is to make A/D converter close to antenna, we should convert IF analog signal even RF analog signal into digital signal. However, limited by the current technical level of the chip, it is difficult to realize RF signal digitalization. Thus, IF signal digitalization becomes the prevalent choice. Today, the technologies of IF signal digitalization is one of technologies be in great progress of Software Radio. IF digitalized receiver has becomes one of the most important parts of radar system. Therefore, it is significant to research into and develop IF digitalized receiver.Firstly, this paper simply discusses the principle of monopulse radar, and the development of digital receiver in and outside, bring forward the monopulse radar IF digital receiver based on FPGA and DSP, and give the work flow of this receiver. Then it studies the theory of IF digital receiver, including the band pass sampling, the quadrature demodulation, the digital down convertor, the multiphase structure of filter and so on.And then, it mainly researches optimization and realization of digital quadrature demodulation receiver. First, it gives the development and application prospect of FPGA, then for some kind receiver parameters, Combining the actual engineering example, according to the concrete demand, design and use the two-level in series FIR filter, realize it in a single field programmable gate array (FPGA) chip, and cosimulate it in ModelSim and Matlab software, the results indicate this kind of receiver absolutely can be used in actual project.Next, it studies on the realization of FFT base on FPGA. to realize FFT of high speed signal in time, it chooses the time-extractive radix-2 FFT-pipeline architecture algorithm. It uses Matlab to verify this algorithm, then design and realize the 16 bits fixed-point pipeline FFT on the FPGA, also it analyses the error of FFT and the design of IFFT. The test results can hold the right frequency characteristic, and the dynamic range is about 70dB,can run at 100MHz, so the design is feasible.In the end, finish the design and realization of some other important modules, and design the top control module for one full receive channel.
Keywords/Search Tags:digitlized receiver, quadrature demodulation, FPGA, FFT, cosimulation
PDF Full Text Request
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