Development Of A Wireless Communication Signal Demodulation Experimental Platform Based On FPGA

In recent years, with the rapid development of FPGA digital signal processing technology and software radio, FPGA applications in the field of communication has been more and more attention. In response to this juncture. In this paper, using FPGA as the main digital signal processing devices, developed a wireless communication signal demodulation experiment platform.communication can be divided into two categories: the first is a single-user multi-standard wireless communications, such as AM, FM etc; the second is a single-standard multi-user wireless communications, such as CDMA, TD-LTE and so on. In order to understand and master the modem on FPGA, in the first category selected FM, AM(analog modulation), 2ASK, 2FSK(digital modulation) four kinds as a demodulation instance, using normalized instantaneous amplitude characteristics,respectively, in the analog and digital modulation to achieve modulation recognition.As we all know that the FPGA implementation of digital modulation demodulation has been extensively studied, so this article only study the implement of carrier synchronization techniques on FPGA. Selected CDMA spread spectrum system in the second category as a demodulation instance.At the same time, finish a hardware experiment platform development which includes digital signal processing board and RF front-end circuitry.Using superheterodyne receiver structure to implement the RF front-end circuit.The main task of RF front-end circuit is to complete signal’s down-conversion process twice and AGC which receive from antenna. Finally, in the output of AGC, a 455 k Hz FM signal can be get. The implementation of the various demodulation algorithms are on the digital signal processing circuit which use the way that A/D converter sampling quantization signal, run algorithms on FPGA, D/A converter reduction signal. Run the FM demodulation program on the experimental platform can clearly hear the FM broadcast.Using the Costas loop to complete carrier synchronization. In the second stage multiplier, adoption an extremely resource-saving approximation to complete multiplication. the results show that the input frequency range from 0-100 k Hz the loop can lock and the greater the difference between the initial frequency the longer the lockout time. Modulation recognition feature of FPGA implementation, use FFT IP core Combined with multi-stage pipeline and a control state machine to implement. Complete simulation of four different signals in Modelsim. The exponent part of different standard signals FFT difference 32 times, hence in analog modulation and digital modulation, can effectively complete the identification.The FPGA Implementation of MMSE multiuser detection algorithm we use Matlaba through PC send data to the FPGA using RS232. Finally, performe Monte Carlo simulation, obtained BER, which between the matched filter and MMSE multiuser detection algorithm theoretical value,taking the quantization and truncation error into account.The algorithm is implemented in the FPGA correctly.