The Research Of Modeling Of Single Electron Transistor Based On Master Equation And Simulation Of Its Circuits

Based on the orthodox theory for the single electron tunneling phenomena, this paper sets up the models for single electron transistor (SET) by two different methods. Both of them are suitable for the simulation of single electron transistor circuits and SET/MOS hybrid circuits.The first method combines the circuit simulator HSPICE with master equation arithmetic. Master equation is built and resolved by choose master states of single electron transistor, and then we add the device model of SET into the HSPICE simulator using the CMI (Common Model Interface) which is a function of HSPICE. After compare the simulation results of SET I-V characteristics with the results of SIMON and experiment data, it is confirmed that the model is accurate and suitable for the simulation and analysis of SET circuits and SET/MOS circuits in a wide range of temperature and bias. The second method also based on the master equation method of single electron transistor. In this paper, a Verilog-A behavioral modeling for SET which is base on a simplified Lientschnig's PSPICE single electron transistor (SET) model is proposed. Utilize this model, SET circuits and SET/MOS hybrid circuits can be simulate by the tool of Cadence Spectre. After SET logic circuit simulation we can be found that, compared with Lientschnig' PSPICE SET model, Verilog-A model is shown to be reasonably accurate and reduce the simulation time a lot. The simulation time is saved by 86.64% on everage. And after extented this model, it can be used to simulate muti-gate SET circuits.In addition, this dissertation researches the possible application of SET in both digital and analog circuits and SET /MOS hybrid circuits. Compared three SET binary full adders based on different logic in terms of the numbers of SET, Vo/Vin, delay times and so on. We analyze the advantages and disadvantages of complementary logic, majority logic and pass-transistor logic design methods which are used in SET logic. The SET AD converter and SET/MOS hybrid DA converter are analyzed and simulated. SET circuits have low dissipation and simple structure. All of the simulations realized expected circuit functions, which further demonstrates the proposed model is valid for SET circuits and hybrid circuits' simulations.