Implementation And Optimization Of JPEG Encoder

In recent years, with the development of microelectronic technology, network communications, multimedia and real-time image processing are widely used in electronic consumables. Digital image compression becomes a new hot-point in information industry.This dissertion mainly introduces the standard of JPEG baseline mode compression, and the architecture, implementation of high speed JPEG encoder, as well as the optimization in speed, area and power consumption. The main work of this dissertion is summarized as follows:First, this article simply introduce the JPEG standard, implement system level model of JPEG encoder using SystemC language and design the SystemC/HDL co-simulation platform.Second, the RTL module is implemented, using Top-Down design method and system level model as reference. The RTL design has high compression speed, for the pipeline architecture.Third, in order to optimize the area and power consumption, the fused constant multiplication and control logic is used in color space convertor. It can save about 30% dynamic power consumption in low sample rate.Forth, quantization and run-length encode are fused to speed up encoding and reduce area.Finally, the RTL level testbench and the verification on FPGA are implemented.The whole design can be used independently and also could be integrated in other system. As JPEG encoder, it can be used in many kinds of electronic consumables such as digital camera, visualphone, cellphone, desktop video, and so on.