Research On The Digital Radar Receiver Algorithm And The Implementation Based On FPGAs

The software radar is the morden radar important development direction. And one of key techniques is realization of digital intermediate frequency receiving system. The dissertation take some radar digitization intermediate frequency receive as a background, the main research based on the FPGA digitized intermediate frequency receiving system, mainly includes based on the scene programmable logic array (FPGA) the single pulse radar digitization intermediate frequency receivingsystem design; The method of survey the velocity of moving target by pulse train; Design the module of the fixed-floating point by FPGA; FPGA hardware resources and processing speed optimized design.The dissertation first analyzed the merit of the radar digital intermediate-frequency receiver by FPGA, and pointed out that FPGA suitablly completed highly effective and the algorithm fixed task; Compares with the special-purpose integrated circuit (ASIC), the FPGA shows more advantages in its flexibility of design, simplicity of system configuration, modification and maintenance.Next, the dissertation is on the research and implementation of single pulse radar digitalized IF receiver by FPGA This dissertation has polyphase filters method, because the computation quantity be lower than the traditional orthogonal frequency mixing method, in addition, this method does not need the orthogonal local oscillation, moreover the following digital filter step number also very low (only needs 8 steps), realizes is extremely simple. High precision AD chip is used for intermediate frequency data sampling and FPGA of Virtex-Ⅱseries is used for the implementation of intermediate- frequency orthogonal system. The DDC realization divides into two parts: I/Q decomposition and filter. This dissertation selects the state machine method, realizes I/Q through the Verilog language compilation module, with clock rise along realization condition control. The design of filters are mainly (uses distributional algorithm) through the filter IP core to realize the filter design, with the Verilog language realization radar intermediate frequency receive sequential control, and has produced FPGA in the resources and the speed some optimized methods and the intermediate frequency orthogonal receive module performance test method. The simulation result indicated that the system is effective and reasonable, definitely may satisfy lradar signal processing, the signal to noise ratio can achieve the anticipated effect.Finally, in order to improve the precision, considering the project realization, survey velocity by pulse train was advanced, improve signal-to-noise ratio by accumulate the pulse train, measure the spectrum of target by range gate-Doppler frequency technique, then, achieving the accurate velocity information of target according to conversion of frequency and velocity. The simulation result indicated that, compare to the method of FIR filter, the former oen took fewer resources, enhanced the signal to noise ratio, moreover points which accumulated through the increase signal pulse, but also was allowed to enhance the precision.