Design Of SpaceWire Node Interface

Future space tasks need to transmit a huge number of data between science instruments, mass-memory units, computer and downlinks, so the communication in the spacecraft must be very exactitude in speed, agility, abnormity managing, fault protection and fault renewing. The spacecraft bus that connects absolute electronic equipments together will be very important. Its speed, agility and reliability will infect the whole performance of the spacecraft directly.SpaceWire is a high-speed, point to point, full-duplex, serial bus network that taking the advantages of FireWire, ATM and Ethernet. Considering the specialty of the space application, SpaceWire is enhanced in EMC(electronic and ground compatible), mistakes searching, abnormity managing, fault protection and fault renewing to meet the needs of future, high capability, high speed data transmission.Firstly, the purpose of the thesis was briefly introduced. The development of SpaceWire was summarized. The characters of SpaceWire and other high-speed bus were also introduced and briefly compared. Secondly, in this design, as the bridge between SpaceWire network and the host, the SpaceWire interface is connected to the APB bus. So, it keeps to the ECSS-E-50-12A standard in the side of the SpaceWire network, but AMBA on-chip bus standard in the side of the host. Because of this, the ECSS-E-50-12A standard and the AMBA on-chip bus standard were described detailed in this thesis. In the following design implementation, the design is modeled at RTL level with Verilog HDL in Top-Down design methodology, and give out a detailed description of the special methods. In the end, utilizing the APB bus function model (BFM) thought, the thesis builds a simulation environment to finish the function verification. In addition, the thesis has achieved the gate level functional and timing verification using gate level netlist and SDF timing information after the logic synthesis of the router design.