Control And Application Of The High Speed Serial Bus

With the development of science and technology, the application range of the radar is more and more wide. People have higher requirement on the properties of radar and radar signal processing algorithm is becoming more and more difficult. This is a new challenge to the hardware platform of signal processing. The traditional radar signal processor employs the VME or CPCI standard,which adoptparallel bus data transmission. But the bottleneck problem of parallel data transfer rate of bus makes them difficult to meet the requirements of at present on a lot of signal processing platforms,which limits its application. The VPX standards which introduced high speed serial bus improve the data transfer between the boards at a high speed. It breaks through the parallel bus transmission bottleneck problems.So the VPX standards get more and more used on signal processing platform.This paper analyzes the content of control and application of the high speed serial bus on a VPX architecture signal processing platform. This hardware platform of the VPX architecture includes FPGA, DSP and Power PC three processors, and three kinds of high-speed serial bus: Rapid IO, PCIe and Rocket IO. The serial Rapid IO bus connects each processor in the form of exchange of interconnection. Rocket IO is used for interconnection among the FPGAs and PCIe is used for interconnection among the Power PCs. This paper will discuss the first two high-speed serial bus.Vx Works operating system runs on Power PC, and the control of the Serial Rapid IO switch chip is based on this operating system. It can realize the enumeration and build the routing table and distribute ID for all the endpoints. The Aurora IP core is tested in this paper and for the Serial Rapid IO IP core, its complex user interface is modified and new interface is suitable for all FPGAs in this platform. It tests the modified user interface and SRIO transmission performance.This paper presents a transmission plan for signal pre-processing based FPGA in view of the specific radar parameters and requirements. It analyzes the concrete application of high speed serial bus in different situations. The data transmission among the endpoints can be 12.5Gb/s and the signal pre-processing function is realized. Stability results of pulse pressure and the results of the coherent accumulation present in FPGA. Optimization is an essential step in engineering implementation, so the paper will propose two optimization schemes in the use of FPGA.At last, the paper work are summarized, and the shortage and the follow-up research work are illustrated.