800MHz-1.2GHz CMOS Adaptive PLL Design

A Phase Locked Loop (PLL) with Analog Adaptive Bandwidth Control (AABC) and an 800MHz to 1.2GHz output range has been designed in this paper. The Adaptive PLL (APLL) can be widely used for Clock & Data Recovery (CDR) or Clock Generation in high-speed data communication systems since its special performance in fast locking and noise immunity.A new-type AABC has been presented based on conventional Charge pump PLL (CP-PLL) circuit. The APLL with AABC block can control the loop bandwidth according to the locking status and the amount of inputs'phase error adaptively; and consequently low-noise and fast-lock performance are achieved. In the design of Phase Frequency Detector (PFD), D Flip Flop (DFF) with the True Signal Phase Clock (TSPC) structure is adopted to satisfy the requirement of a hundred megahertz input frequency. And a delay cell is added in PFD to eliminate Dead Zone. Furthermore, the dual-delay path technique is adopted in Voltage Controlled Oscillator (VCO) design to implement high oscillation frequency and obtain a wide tuning range.Based on Chartered 0.35μm EEPROM process, the APLL is designed by means of Top to Down design method. The stability analyse of APLL has been done using Matlab. Then, the essential blocks and the whole circuit have been design in schematic and simulated using Cadence Spectre RF.In all five process corner, the designed APLL satisfies an 800MHz to 1.2GHz output range and a 2μs maximum settling time. Working at 1GHz, the phase noises are–93dBc/Hz at 500 kHz offset, and the whole circuit draws 7.2mA current from 3.3V supply. Furthermore, the fast locking and noise immunity characteristic are verified by contrasting APLL and conventional CP-PLL. The simulation results show that the designed APLL realizes the function of adaptive bandwidth control and meets the design specification.