Research Of High-speed On-line Machine Measuring Method

Product quality detection is important in automatic production. High-speed on-line detection system based on machine vision detection technology is the preferred solution. Thesis analyses the machine vision technology and its development statuses at home and abroad, gives the realization method of the embedded high-speed on-line machine vision measuring system with the high-speed DSP chip, high-integrated FPGA chip, and the suited software algorithmic. The technology of software algorithmic realized by hardware and the technology of DSP and FPGA chips'seamlessly links insure the system working high-speed, real-time, and precisely, and these technologies laid a solid foundation for the needs of automated production lines. During the realization, the important work and innovations are:a) Thesis researches the suited image processing technology used in the high-speed on-line measurement system, discusses image preprocessing, feature extraction, and determines the specific realized method, using Sobel operator to achieve a highly efficient image processing algorithm for detection.b) Thesis researches the technology of the key algorithm realized by FPGA in image analysis processing. The system selects Xilinx's FPGA chip of Spaartan3E family, makes full use of internal resources to achieve system chip core algorithm high-speed operation, and makes necessary functional verification and integrated simulation with ISE integrated development environment.c) Thesis researches the technology of algorithm realization and optimization by DSP chip. The system selects TI's TM320C642 chip which has high-speed, parallel multi-stage pipeline and improves the system's running speed effectively.d) Thesis researches the seamless integration technology between the DSP software algorithm and the FPGA core algorithm. The system realizes the seamless integration between the DSP and FPGA with the repeated IP technology, high-speed FIFO structured by the FPGA, and the communications interface realized by EDMA between DSP and FPGA, which improve the image processing speed and system flexibility.