The Study Of High-Speed Image Processing For Machine Vision And Implementation With FPGA

Machine vision has found an increasing application in the field of industry detection system. With the fast development of computer technology and extending of the application, digital image processing is faced with challenges of pursuing high speed and increasing complexity, in which high performance computing, especially parallel computing acts as a very important role. Image processing develops quickly with parallel computing techniques for microprocessor, inexpensive image sensor and new technology for storage.Image data structure and computing complexity cause the problem faced by high speed image processing. According to processing levels of ordinary digital image, image processing is described from three concept levels including data processing level, information extracting level and knowledge level.This paper studies the design and realization of parallel algorithm for special filter. The algorithm and system structure for image processing have changed quickly. Data processing level has large quantities of primitive data, which will be repeated use in process. Algorithm in this level is simple and regular, so that it is suitable to use FPGA hardware platform for its implementation.A frame storage architecture for neighbor operation is captured using DRAM and FPGA. The address controller and the converter are described by the Verilog hardware descriptive language. The design of Two-dimensional discrete convolution is based on the structure of DA-Fir using design tool - Xilinx Coregenerator. The designs are functionally and performance validated through Synthesis and Simulation testing.In the paper, the designing method, function and principle of Verilog HDL design are discussed, the basic principle and FPGA technology also be explained, the hardware design of FPGA test board is introduced, schematics is completed.In the end some ideas are put forward for further research.