Realization Of Ring Bus Based On LVDS And Its Application On Test Bench For Radar Signal Processor

As the functions of testing system become more and more complex, traditional parallel bus cannot satisfy the demand of high-speed and real-time data communication any more, which has turned to be the bottleneck of the whole system. Transmitting data in serial method, Low Voltage Differential Signaling (LVDS) has the merits of low noise and consumed powers, while the ring bus has the advantages of high efficiency and fair access. So, the combination of these two buses becomes one of effective approach to solve the problem.Based on the advantages of LVDS and ring bus in high-speed communication system, serial ring bus based on LVDS is put forward. The realization of protocol and maintenance of logic ring are introduced in detail. The characteristics of the serial bus are highly real-time, highly dependability and a little synchronous error in multi-load communication system.This dedicated bus has been applied in a radar signal simulator successfully. The thesis mainly focuses on definition of the bus, selection of connectors and high-speed data transmission logic design for the interface modules. At last, hardware circuit and time sequences among modules are introduced. The key technologies in this thesis are as follows:(1)By quantitatively analyzing the influence of traditional method on communication speed, multi-form serial data transmission is used in the system to improve the reliability of the system and the transmission rate.(2)By adopting high-speed buffer integrated in FPGA, the speed inconsistency between data storage and processing is improved in maximum.(3)The adaptive ring connection of bus is realized by hardware, which can meet the different needs of expansion. According to the different types of data, a fixed volume of data circulatory writing and broadcasting technology are adopted, which can increase the data transmission speed inside the system greatly. The FPGA is used as the flat of exploitation in this design. All the modules are completed in the FPGA. The structure and principle of the agreement as well as their realization are introduced in detail. As proved in practical application, the bus can realize high-speed and real-time communication by using serial interface and simple logic.