Research Of Synchronization Of Downlink Of WCDMA And Realization In FPGA

It is well known that synchronization technology is very important to most telecommunication systems, and as one criterion of 3rd telecommunication WCDMA is important enough for us to look into the synchronization of it. As FPGA is playing a quite important role in most hardware systems, it's quite necessary to study how to realize the synchronization of WCDMA.This paper discusses the arithmetic of cell search and does the related simulation. Then it pays lots of attention to the arithmetic migration in FPGA.This paper compare and discuss some kinds of arithmetic according the criterion of complexity and speed of computing, and then do migration in FPGA to complete a stint and stable hardware system. At last, it proposes to use improved PSC matching filter in PSCH with realization of pointer-double-ram in FPGA; to use improved PFHT and looking-up judging with integrated logical realization in FPGA; to use shift-memory to generate scrambling code and scoring judging method.The design of this paper skillfully utilizes the parallel architecture of FPGA to minimize the sources the system occupying comparing to other synchronization systems in FPGA. As a result, we realize the cell search on V4 chip of XILINX with only 500 slices. It provides an efficient way of small modeling in FPGA.