Synchronization Principle And FPGA Implementation Of WCDMA Downlink System

Synchronization is a key technology in mobile telecommunication system. Synchronization is indispensable in the process of communication and it has a significant impact on system performance.WCDMA, as one of the 3rd generation mobile communication standards, has been world-wide adopted. Cell search is a critical physical-layer procedure, which can synchronize mobile station and base station in downlink.As one of semi-custom circuits, field programmable gate array (FPGA) solves drawbacks of full-custom circuits and original PLD (programmable Logic Device). With the programmable ability and short-develop-time feature, FPGA gradually becomes one kind of ASIC circuits with short design period, low develop fund and little risk.Therefore, it is of theoretical and practical significance to study WCDMA synchronization algorithm, its FPGA implementation and verification. This paper first introduces WCDMA physical layer technology and then describes in detail the principles of WCDMA primary, secondary and pilot synchronization. Improved algorithms of the first two step synchronization have also been introduced and proved. Comparison to traditional algorithm is done in terms of rescource utilization and complexity. Float-point simulation results and analysis are also given. After that, implementation of downlink synchronization is discussed based on FPGA (V4-SX-35), compuatation flows and interface design of modules are also presented. Finally, FPGA verification method of design modules is introduced.In this paper, a thorough discussion of WCDMA downlink synchronization algorithm and FPGA design is given. Simulation results of both matlab and modelsim are presented. FPGA implementation of the discussed modules are realized with low complexity and resource overhead, while achieving system design requirements.