A Study For The Parasitic In IC-Packaging

In recent years, semiconductor revolution drives the chip clock frequency getting more fast and fast and the noise margin for device becomes narrower than before. At same time IC Packaging technology is moving toward to system packaging, which is from board level system to IC package level system. We have to pay attention to IC package interconnection for wire and trace, because the signal will not be transparent at high frequency. All the interconnection is not simply regarded as a transmission line without any resistance, capacitance, inductance and conductance.Signal can be described in time domain and frequency domain; it can be mutually converted between each other by Fourier Transfer. With Spice tools, it can be clearly understood that there will have more and more the effective highest sine-wave-frequency components as device rise time decrease. The device bandwidth has strong relation with the rise time of the device. The bandwidth of an interconnection refers to the highest sine-wave-frequency component that can be transmitted by the interconnection without significant loss. All the interconnections have bandwidth due to signal have attenuation in signal transmission at different frequency. This article analyzed the physics of the resistance capacitance, inductance and conductance of interconnect. The resistance of interconnect have strong relation with the conductivity of the material, the cross-section of the interconnection, and length. In high frequency, the resistance of the interconnection depends on the skin depth of the current. The interconnections of the wire and trace also have capacitance with return path, and mutual-capacitance with other interconnects. This article also mentions how to calculate the effective dielectric for the material. Inductance is the most important factors for signal integrity. It includes the self-inductance the mutual-inductance. When calculate the inductance of the interconnection, it should refer to the return path. In order to reduce the inductance, we need to put the signal path close to the return path, and reduce the trace or wire length. In high frequency, it also have conductance at dielectric material due to dissipation factor of the dielectric material causing the current leakage.Paksi-E is 3-D quasi-static field solver for 3-D IC Package parasitic RLGC extraction, by simplifying the Maxell's Equation. Paksi-E solve equation for the finite element to get the result by meshing the wire and solderball and trace with 3D. A real example with IC package was used to analyze to RLGC with Paksi-E and Cadence Allegro software, and extract RLGC data, and get package IBIS model. The critical signal such as clock signal was taken for analysis. A simple model was made by Spice software for analysis. We can see that as frequency go higher, the signal rise time edge will increase because of the parasitic in the package. It has limitation to optimize all the nets parasitic only by optimizing the substrate routing if the package I/O is fixed. The package designer should co-design with IC designer and PCB designer to effectively provide less parasitic package for board level system.