Low Power VLSI Implementation Of JPEG Image Compress Algorithm

Image is an important measure for mankind to obtain information. Along with the development of the electronics, micro-electronics, computer and communication technology, digital image has become the main information storage and transmission way. In order to solve the problem of huge digital image data of the storage and transmission, digital image compression technology emerges as the time require. This paper chooses the compression technology of the JPEG standard as its research target. On the basis of further analysis of the baseline algorithm modules of JPEG standard, the codec system of JPEG baseline system has been implemented in VLSI way. Especially the key modules of JPEG standard algorithm are improved and optimized in order to get a good cost of area and power dissipation.The design adopts the binDCT algorithm for the basic compression system based on JPEG standard in order to reduce the cost of implementation. Comparing it with other algorithm in performance through MATLAB simulation, it proves that the performance of binDCT's C3 level is close to other algorithm, and it can reach the requirement of design. The algorithm is modeled and simulated using MATLAB. In the stage of VLSI implementation, both RTL code and netlist are fully verified. The testbench. and testcases are carefully designed to cover all possible scenarios. The result shows that the data is consist with the result processed by MATALB reference model; It can do the functions required and its coverage also reaches the design requirement.Power is another key concern. To save power, clock gating and other methods in RTL level are used. Some methods in netlist level with assistant of the EDA tools can reduce power dissipation as well. Through analyzing the data which is got from gate level simulation with timing info annotated, the methods can reduce power dissipation effectively.